In the present digital radiography system, a 30 frame per second vidicon camera produces streams of analog data indicating the intensity of the viewed radiographic imagery, and applies such signals to an analog to digital converter which thereafter produces binary words, each word representing each picture element or pixel of each picture frame. These words are applied to the input of a pipeline circuit which, in conjunction with an ALU performs processing in real time on the picture elements of each frame, and after such processing, ultimately causes analog signals to be applied to a CRT circuit which are representative of the final digital output signals from the data processing system. These operations performed in real time, include time interval differencing, edge enhancement, enhancement of high spatial frequency images and the like. Since it is of utmost importance to operate upon the picture elements representing the viewed images in real time, pipeline circuitry is employed in conjunction with RAMS which store the digital words making up each frame of pixels or picture elements, to facilitate processing. During design of the pipeline circuitry, it was deemed desirable to input and output each pixel words through the pipeline circuitry, one word during each 120 ns clock period. However, the random access memory within the pipeline, which was desired for the design, required a minimum response time for readin, and for readout operations, each of which exceeded the 120 ns clock period. In other words, since real time processing of 30 frames per second is required, readin and readout of 30 frames or arrays of picture elements, each element represented by a 12 bit word, must be performed in each second. However RAMS were not available which could operate at a higher clock frequency then clocks having a period of 160 ns, so that straight forward inputting of the words could not be performed at a data rate higher than the rate constrained by the minimum 160 ns pulse period required to operate the RAM within the pipeline. Thus, what was desired was to process one 12 bit word pixel through the pipeline every 120 ns, even though the minimum RAM response time was substantially longer.